Stripline Impedance Calculator (IPC-2141)
Characteristic impedance for a trace buried between two ground planes, per IPC-2141.
- Impedance
- 45.82 Ω
- Formula
- IPC-2141A stripline
IPC-2141A stripline: Z₀ = (60 / √εr) × ln(4·H / (0.67·π·(0.8·W + T))).
H is the total dielectric height between the two reference planes. Trace is centered vertically between them. Stripline is fully embedded in a homogeneous dielectric, so εr acts directly (no effective-εr correction like microstrip).
Stripline vs microstrip
Stripline puts the signal trace between two ground/power planes on inner layers. This gives tighter impedance control, near-zero EMI radiation, and better crosstalk isolation, at the cost of two extra layers and no visual access for probing/rework. Use stripline for critical high-speed signals (DDR, PCIe, SerDes); microstrip for most other controlled-impedance nets.
Common stripline stackup
6-layer board with signal-ground-power-power-ground-signal is the classic controlled-impedance stackup. Inner signal layers use stripline; outer layers use microstrip.
Frequently asked
- What is stripline impedance?
- The characteristic impedance of a trace sandwiched between two ground/power planes on inner PCB layers.
- Why is stripline better than microstrip for high-speed?
- Fully enclosed by ground planes: near-zero EMI radiation, tighter impedance control, less crosstalk. The trade-off is two extra layers and no probe access.
- Can I mix stripline and microstrip?
- Yes — a common approach is microstrip on outer layers for probeable/high-density signals and stripline on inner layers for critical high-speed nets.
- How do I hit 50 Ω stripline on FR4?
- Depends on total dielectric height between planes. On a 6-layer stackup with ~0.5 mm plate-to-plate spacing, a 0.2 mm trace lands roughly at 50 Ω.
Stripline sits on an inner layer between two planes, so it needs four layers or more. PCBEditor builds 4, 6 and 8-layer boards from a description.
Route inner-layer stripline on a real board →Related free tools
- Microstrip Impedance Calculator (IPC-2141)Characteristic impedance for a trace on an outer layer above a ground plane, per IPC-2141.
- Differential Pair Impedance CalculatorDifferential and common-mode impedance for edge-coupled microstrip and stripline pairs (USB, Ethernet, LVDS).
- PCB Layer Stackup Planner (2/4/6/8-Layer)Plan a PCB layer stack with copper weights, dielectric heights, FR4 Dk values, and finished thickness — 2 to 8 layers.